A scrambler is known from the CCITT recommendation G.709 number 2.4 and FIG. 2.10, which is able to scramble data streams that must be scrambled in a pseudorandom sequence, which is generated in accordance with the forming principle D.sub.i =1+D.sub.6 +D.sub.7. According to the CCITT recommendation, such a pseudorandom sequence can be produced by the type of shift register shown in FIG. 2.10. In the illustrated shift register, the outputs of the last two storage cells are linked to each other by an exclusive OR-gate, and the output of the exclusive OR-gate leads to the input of the first shift register. Here D.sub.i is the binary value at the input of the shift register, D.sub.6 the binary value at the output of the next-to-last storage cell, and D.sub.7 the binary value at the output of the last storage cell.
According to the CCITT recommendation G.709, a serial data stream to be transmitted must be scrambled in accordance with the above named forming principle.
It is now known to convert serial data streams into parallel partial streams for data streams with a high bit rate frequency, and to link the partial streams by modulo-2 addition in such a way, that a subsequently reconverted serial data stream is scrambled with the desired pseudorandom sequence. For several decades the required pseudorandom sequences for the modulo-2 addition of the partial streams have been produced by a feedback shift register with a downstream network. Improvements of parallel working scramblers were always sought by optimizing the downstream network.
It is known from PROC. IEE, Vol. 111, No. 11, November 1964, pages 1803 to 1806 by S. H. Tsao et al, to produce a pseudorandom sequence of finite length in a feedback shift register. A low depth shift register is used, in which further random sequences with a different phase relation are produced from directly acquired pseudorandom sequences through modulo-2 addition in a downstream network. The arrangement of the network allows the acquisition of more pseudorandom sequences than exist in the outputs of the shift registers. The network consists of exclusive OR-gates, in which the modulo-2 addition is performed. The network is optimized so that the lowest number of modulo-2 additions needs to be performed to produce a determined number of pseudorandom sequences with a different phase relation, to bring about as short a time delay as possible from the production of the additional pseudorandom sequences in the network.
In a report published ten years later by Siemens Research and Development, volume 3 (1974) no. 4, pages 218 to 224, the basic idea published by S. H. Tsao et al is used with the shift and addition properties--when two cyclically shifted versions of the same pseudorandom sequence with overlapping bits is modulo-2 added, the result is another cyclically shifted version of the same pseudorandom sequence. It was shown that the use of certain calculation principles permits one to simply and generally determine the required linkages for a definite predetermined structure of a pseudorandom sequence. The basic idea was pursued, that an N-stage shift register L=2.sup.N -1 can produce similar pseudorandom sequences with a different phase relation.
scramblers are known from part 1 of a report published nine years later in Elektronik 26/30.12.1983, pages 67 to 70, entitled "Parallel working scrambler, descrambler and random sequence generators", in which the idea is still being pursued to create similar pseudorandom sequences, but which are phase shifted with respect to each other, from an N-stage shift register L=2.sup.N -1.
Particularly suitable linkages for parallel working multiplicative scramblers are indicated.
The disadvantage of the known solutions lies in that modulo-2 additions performed in series in a network require a minimum cycle period, which limits the maximum bit rate frequency.